Commercial RISC-V Reference Platform
Current Active Commercial Project (2025)
Trade Show Demonstrator in Development
Supporting a commercial RISC-V IP provider in developing a reference platform integration for their first RISC-V processor on FPGA. This integration serves as a demonstrator for trade shows, client engagements, and sales activities.
Project Overview
Client: Commercial RISC-V IP Provider (Confidential)
Timeline: Q1 2025 - Today (Ongoing)
Type: Commercial RISC-V integration project
Objective: Build a functional and scalable reference integration of the client's RISC-V processor IP, including essential peripherals and development infrastructure, on FPGA hardware.
Project Goals
Build a functional and scalable reference integration showcasing:
- The client's RISC-V processor IP capabilities
- Complete peripheral ecosystem
- Development tools and workflows
- Demo applications for trade shows and customer engagement
- Technical reference for client internal teams
Key Deliverables
CPU Integration
Dual RISC-V CPU Architecture:
- Andes RISC-V CPU - Commercial RISC-V core integration
- Synopsys RISC-V CPU (ARC-V) - Additional commercial core
- Validation of both CPU cores on FPGA platform
- Performance benchmarking and optimization
Peripheral Integration
Complete System-on-Chip Ecosystem:
- DDR memory controller integration
- SRAM interfaces
- UART (serial communication)
- SPI (Serial Peripheral Interface)
- I²C (Inter-Integrated Circuit)
- JTAG debug interfaces
- GPIO (General Purpose I/O)
- AXI and Wishbone bus architectures
Development Infrastructure
Automated Workflows:
- FPGA synthesis automation
- Deployment workflows
- Verification and testing frameworks
- Continuous integration pipelines
Bootloader & System Software
- Initial bring-up of bootloader
- Device tree configuration
- Driver development for peripherals
- Demo application development
Documentation & Support
- Technical documentation for client teams
- Integration guides
- Reference designs
- Customer demonstration materials
FPGA Platforms
| Platform | Series | Usage |
|---|---|---|
| AMD Xilinx Kintex-7 | 7-Series | Primary development platform (Genesys 2) |
| AMD Xilinx Ultrascale+ | Ultrascale | Advanced features and performance |
Technologies & Tools
Hardware
- Genesys 2 - AMD Kintex-7 development board
- Ultrascale+ - High-performance FPGA platform
- Multiple I/O interfaces for peripheral connectivity
IP Cores
- Andes RISC-V CPU - Commercial processor IP
- Synopsys RISC-V CPU (ARC-V) - Additional processor option
- Synopsys Peripheral IPs - Commercial IP building blocks
- Open-source modules - UART, SPI, I²C, AXI, Wishbone
Development Tools
- Open-source toolchains - Compiler, debugger, simulator
- Vivado Design Suite - FPGA synthesis and implementation
- Segger debuggers - JTAG debugging infrastructure
- Custom automation scripts - Build and deployment workflows
Project Approach
Phase 1: Requirements & Architecture
- Analysis of client CPU IP specifications
- System architecture design
- Peripheral selection and planning
- Resource estimation and planning
Phase 2: Core Integration
- RISC-V CPU integration into FPGA
- Validation of CPU functionality
- Performance testing and optimization
- Debug infrastructure setup
Phase 3: Peripheral Ecosystem
- Memory controller integration (DDR, SRAM)
- Communication interfaces (UART, SPI, I²C)
- Bus architecture (AXI, Wishbone)
- GPIO and debug interfaces (JTAG)
Phase 4: System Software
- Bootloader development
- Device tree configuration
- Driver development
- Operating system bring-up
Phase 5: Demo & Documentation
- Demo application development
- Performance benchmarking
- Technical documentation
- Trade show preparation
Current Status
Active Development (2025)
Status: In progress
Completed: - Andes RISC-V CPU integration ✅ - Synopsys RISC-V CPU integration ✅ - Core peripheral set integrated ✅ - Bootloader and device tree operational ✅ - Automated synthesis workflows ✅
In Progress: - Demo application development 🔄 - Documentation finalization 🔄 - Trade show preparation 🔄
Technical Achievements
Dual CPU Architecture
Successfully integrated two different commercial RISC-V cores on the same platform:
- Demonstrates flexibility of RISC-V ecosystem
- Allows direct comparison of different IP options
- Provides customers choice based on their requirements
Comprehensive Peripheral Set
Complete system-on-chip functionality:
- Memory hierarchy (DDR, SRAM)
- Standard communication protocols
- Debug and development infrastructure
- Extensible for customer-specific peripherals
Automated Workflows
Production-ready development environment:
- One-command FPGA synthesis
- Automated testing and verification
- Continuous integration ready
- Reproducible builds
Value to Client
Customer Engagement
- Trade show demonstrations - Working RISC-V system for exhibitions
- Customer evaluations - Reference platform for potential clients
- Sales support - Proven implementation to accelerate deals
Technical Validation
- IP validation - Proves CPU IP works in real systems
- Performance data - Benchmarks for customer presentations
- Integration knowledge - Documents how to use their IP
Documentation & Support
- Reference design - Starting point for customer implementations
- Integration guides - How to use client IP effectively
- Technical support - Documentation for internal teams
Lessons & Best Practices
Multi-Core Integration
- Handling multiple RISC-V cores requires careful architecture planning
- Vendor-specific peripherals need adaptation for different CPUs
- Debug infrastructure must support multiple cores
Commercial IP Integration
- Working with commercial IP providers requires:
- Understanding licensing and usage terms
- Coordinating with vendor support teams
- Managing IP updates and versions
- Documentation and knowledge transfer
Reference Platform Development
- Must balance:
- Comprehensive features vs. simplicity
- Performance vs. resource usage
- Flexibility vs. ease of use
- Documentation completeness vs. timeline
Impact on Motius Capabilities
This project strengthens our:
Commercial RISC-V Experience: - Proven ability to integrate commercial IP (Andes, Synopsys) - Established relationships with major IP providers - Understanding of commercial IP workflows
Multi-Core Systems: - Experience with multiple RISC-V cores on single platform - Comparative analysis of different RISC-V implementations - Architectural decisions for multi-core systems
Customer-Facing Deliverables: - Trade show demonstration experience - Reference platform development methodology - Technical documentation best practices